<html>
<head><meta charset="utf-8"><title>zicsr extension on riscv32imc · t-compiler/risc-v · Zulip Chat Archive</title></head>
<h2>Stream: <a href="https://rust-lang.github.io/zulip_archive/stream/250483-t-compiler/risc-v/index.html">t-compiler/risc-v</a></h2>
<h3>Topic: <a href="https://rust-lang.github.io/zulip_archive/stream/250483-t-compiler/risc-v/topic/zicsr.20extension.20on.20riscv32imc.html">zicsr extension on riscv32imc</a></h3>

<hr>

<base href="https://rust-lang.zulipchat.com">

<head><link href="https://rust-lang.github.io/zulip_archive/style.css" rel="stylesheet"></head>

<a name="229656065"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/250483-t-compiler/risc-v/topic/zicsr%20extension%20on%20riscv32imc/near/229656065" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Henri Lunnikivi <a href="https://rust-lang.github.io/zulip_archive/stream/250483-t-compiler/risc-v/topic/zicsr.20extension.20on.20riscv32imc.html#229656065">(Mar 10 2021 at 13:21)</a>:</h4>
<p>TL;DR: does <code>zicsr</code> exist on riscv32imc and should that be available via rustup?</p>
<p>I'm investigating compiling Rust on a simulated PULPissimo chip with an Ibex core for research. This platform implements riscv32imc. The existing build system uses a modified RISC-V GCC 7.1.1 to compile C that is linked with a runtime library supplied by upstream.</p>
<p>If I build a binary using the nightly rustc via rustup with target=riscv32imc-unknown-elf and link it using the old build system's linker &amp; upstream configurations, the simulated core throws "Illegal Instruction" at encountering a particular instruction: <code>csrwi</code> a.k.a. some form of a "write control status register". Compiling the C-source with the existing system runs alright, including that same instruction: <code>csrwi</code>, located in the linked upstream runtime library.</p>
<p>I traced the instruction to the RISC-V specification and to an extension called "zicsr" a.k.a. "control status register instructions", and thus suspect that not having this enabled in the rustc/LLVM backend may be my root cause for why the simulator throws "Illegal instruction". Calling <code>rustc --target=riscv32imc-unknown-none-elf --print target-features</code> verifies that rustc is not aware of an extension called "zicsr".</p>
<p>Now, my questions are: could I be on the right track with my suspected root cause or could it just be that my linkage is way dangerous, does the missing "zicsr" make sense, is it possible to add that feature, and how hard would that be (yeah, YMMV)?</p>



<a name="229656720"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/250483-t-compiler/risc-v/topic/zicsr%20extension%20on%20riscv32imc/near/229656720" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> nagisa <a href="https://rust-lang.github.io/zulip_archive/stream/250483-t-compiler/risc-v/topic/zicsr.20extension.20on.20riscv32imc.html#229656720">(Mar 10 2021 at 13:25)</a>:</h4>
<p>Target features can only control (enable or disable) emission of instructions. I would be surprised if it could have a global effect on whether the same instruction works or faults.</p>



<a name="229658309"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/250483-t-compiler/risc-v/topic/zicsr%20extension%20on%20riscv32imc/near/229658309" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Henri Lunnikivi <a href="https://rust-lang.github.io/zulip_archive/stream/250483-t-compiler/risc-v/topic/zicsr.20extension.20on.20riscv32imc.html#229658309">(Mar 10 2021 at 13:33)</a>:</h4>
<p>The call to <code>csrwi</code> instruction is located in the runtime library, the code for which is emitted by the existing build system which probably has the feature. It's linked in with the minimal Rust binary also using the existing build system's linker. It's strange that going through the <code>cargo</code> build system somehow changes the resultant simulator behavior here.</p>
<p>It's good to have confirmation anyway that the target feature only affects emission of instructions.</p>



<a name="229658924"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/250483-t-compiler/risc-v/topic/zicsr%20extension%20on%20riscv32imc/near/229658924" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Henri Lunnikivi <a href="https://rust-lang.github.io/zulip_archive/stream/250483-t-compiler/risc-v/topic/zicsr.20extension.20on.20riscv32imc.html#229658924">(Mar 10 2021 at 13:37)</a>:</h4>
<p>To be clear: since the features should not have an effect on this, the problem is likely in the hardware platform. There's some 2-way interaction between the hardware simulation configuration and code generation, so it's entirely possible there's something wrong there that has nothing to do with the riscv32imc target of Rust/LLVM.</p>



<a name="229659237"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/250483-t-compiler/risc-v/topic/zicsr%20extension%20on%20riscv32imc/near/229659237" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> nagisa <a href="https://rust-lang.github.io/zulip_archive/stream/250483-t-compiler/risc-v/topic/zicsr.20extension.20on.20riscv32imc.html#229659237">(Mar 10 2021 at 13:39)</a>:</h4>
<p>I think the more plausible reason is that your binary does not have the C runtime initialization objects linked in or something along those lines.</p>



<a name="229659367"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/250483-t-compiler/risc-v/topic/zicsr%20extension%20on%20riscv32imc/near/229659367" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> nagisa <a href="https://rust-lang.github.io/zulip_archive/stream/250483-t-compiler/risc-v/topic/zicsr.20extension.20on.20riscv32imc.html#229659367">(Mar 10 2021 at 13:39)</a>:</h4>
<p>Because you're building with a <code>unknown-none-elf</code> target</p>



<a name="229660057"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/250483-t-compiler/risc-v/topic/zicsr%20extension%20on%20riscv32imc/near/229660057" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Henri Lunnikivi <a href="https://rust-lang.github.io/zulip_archive/stream/250483-t-compiler/risc-v/topic/zicsr.20extension.20on.20riscv32imc.html#229660057">(Mar 10 2021 at 13:43)</a>:</h4>
<p>Thanks for the tip! Sounds very reasonable.</p>



<a name="229662477"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/250483-t-compiler/risc-v/topic/zicsr%20extension%20on%20riscv32imc/near/229662477" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Henri Lunnikivi <a href="https://rust-lang.github.io/zulip_archive/stream/250483-t-compiler/risc-v/topic/zicsr.20extension.20on.20riscv32imc.html#229662477">(Mar 10 2021 at 13:56)</a>:</h4>
<p>The _start &amp; _entry areas of the built assembler look fine at least. I believe the runtime library supplies the C run time initialization code. The original C-source is compiled with <code>-nostartfiles</code>. The Rust code also executes fine in the simulator up until the control-status register access (after/within _entry and _start). It feels like it's an issue with setting up the hardware control status registers :S</p>



<a name="229731181"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/250483-t-compiler/risc-v/topic/zicsr%20extension%20on%20riscv32imc/near/229731181" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Henri Lunnikivi <a href="https://rust-lang.github.io/zulip_archive/stream/250483-t-compiler/risc-v/topic/zicsr.20extension.20on.20riscv32imc.html#229731181">(Mar 10 2021 at 19:51)</a>:</h4>
<p>I got it! If I use rustc to compile into object files only, then return to the existing toolchain, I'm able to create functioning binaries. So somehow using cargo breaks something somewhere even if cargo is instructed to use the linker from the existing toolchain.</p>



<hr><p>Last updated: Aug 07 2021 at 22:04 UTC</p>
</html>